Fault Tolerant Nanoscale Structures and Related Delay

Redundancy is a method in the system for designing fault tolerant structure with the Nanoscale gate in electronic systems. Until now, many ways are represented for this purpose, which increases complexity or decreases the system's reliability. In this paper, we compare two methods for designing a fault-tolerant structure with Nanoscale gates. These ways are NAND Multiplexing (NM) and Averaging Cells (AC). The results of simulation that evaluate the area cost and reliability of the gates indicates that NM based gates are more reliable than AC gates when the error probabilities of the circuit parts are lower than 0.003. However, when this value is exceeded (which is expected for electronic nanotechnologies), AC gates are more reliable at a lower area cost. In this paper, we show comparing the NM and the AC in the aspect of the delay parameter. It indicates that the AC method has a constant delay, but the NM system's delay will rise with increasing redundancy. As a result, the AC method's overhead for designing a fault-tolerant system with the Nanoscale gate is lower than the NM method in the aspect of the area and delay time with better reliability.


Introduction 1
Due to the foreseeable limitations of the silicon-based technology and the promising results of new devices of different nature working at the nanometer level, there is worldwide attention to the research and development of modern electronic devices that could be the base of this future technology [1] [2].
Nanowire Field-Effect Transistors (NWFETs) is structured to replace the conventional planar MOSFET channel with a semiconducting nanowire. In these nanodevices, current flows through the nanowire or is pinched off under the control of the voltage on the gate electrode, which surrounds the nanowire. For this reason, they are also known as "gate-all-around" transistors. However, because of their small size, single nanowires can't carry enough current to make an efficient transistor. Researchers are currently working on the gate-all-around transistor architectures based on a small forest of nanowires controlled by the same gate and acting as a single transistor [3,4].
Tunnel Field-Effect Transistors (TFETs) are gated reverse-biased p-i-n junctions whose switching 1. Corresponding Author Email: mlabaf@eng.ui.ac.ir behaviors expected to be much steeper than the conventional MOSFETs that have 60 mV/Dec subthreshold swing at room temperature. Power dissipation is one of the main limitations of the future nanoelectronic circuits. Decreasing the supply voltage reduces the energy required for switching. Still, current FETs require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. TFETs avoid this limit by using quantummechanical band-to-band tunneling, rather than a thermal injection, to inject charge carriers into the device channel [3,5].
We clarify the meaning of three different terms in computing technology, which are strictly related to the system reliability analysis, namely defect, fault, and error. A defect is a physical problem with a final manufactured system that differs from the intended design due to an imperfect fabrication process. A fault is an incorrect state of a system due to the manufacturing defects, component failures, environmental conditions, or even improper design. A fault is active when it causes an error, otherwise, it is dormant. Error is an incorrect output of a system. The cause of an error is always a fault [3].
Electronic gates exhibit a specific error rate due to several uncertainty sources cosmic. The shrinking of the electronic devices near the atomic scale, [6] increases the effect of these error sources. Therefore, as electronic technology goes into the deep Nanoscale, the device reliability decreases rapidly [6]. The power supply voltage scaling that reduces the maximum density of dissipated energy reduces the noise margins too. This can lead to extremely low signal-to-noise ratios (approaching 0-1 dB [7]) and increases the gate sensitivity to device parameter variation, which is currently a cause of yield reduction [8]. It is expected to become even more relevant in the near future [9]. Predictions for Nanoscale technologies indicate that the device reliability will decrease several orders of magnitude [10] so that current implementations confirm this tendency [11].
To build reliable electronic systems using electronic nanotechnologies, it is necessary to include fault and defect tolerant capabilities into the electronic systems.
In the nano CMOS circuit, faults occur at three levels, such as gate level, circuit level, and switch level. Paper [12] discusses the switch level faults of stuckopen or stuck-off and stuck-short or stuck-on that frequently occurs in CMOS switches.
The error sources have very different characteristics and ways to affect the victim gate. Therefore, the design of a reliable system will require several layers of different tolerant techniques [2]. Current tolerant mechanisms use hardware redundancy to detect and/or correct the errors. The most utilized techniques are NAND Multiplexing (NM) and majority voting gates, as proposed by von Neumann [13] in 1955. More recent methods based on Averaging Cells (AC) [14]- [16] and reconfiguration [17] have also been proposed.
In this paper, we compare two fault-tolerant architectures in two ways that can be used to build a first tolerant layer of logic Nano gates. Therefore, the best techniques for this level are NM (as indicated in the comparison presented in [18]) and AC (due to its simplicity). To compare both structures, we first define layouts for NM and AC NAND gates using molecular Nanodevices. To evaluate the reliability of the resulting gate considering the fabrication complexity [1] introduced Nanoscale oriented models able to estimate the error probabilities of each part composing the circuits according to their fabrication complexity. Using the physical dimensions of the gates obtained from the layouts and the proposed models [1] calculate the area cost and the error probability for those gates. Simulation results in [1] indicate that NM based gates are more reliable than AC gates when the error probabilities of the circuit parts are lower than 0.003. However, when this limit is exceeded (which is expected to be the case for electronic nanotechnologies), AC gates are more reliable at a much lower area cost.
Another parameter is the delay, which we calculate for NAND gates in both NM and AC methods. The area cost and the reliability analysis have been presented previously in [1]. In this paper, we show comparing the NM and the AC in the aspect of the delay parameter.
Computing this parameter is important for the different levels of redundancy.
The paper is organized as follows: Section 2 and 3 describe the basic principles of both NM and AC faulttolerant techniques in addition to the physical implementation for each method. Section 4 compares NM and AC in the aspect of delay. Finally, section 5 concludes.

NAND Multiplexing Structure (NM)
An NM gate replicates all the elements of the primary logic function. It adds two extra sets of redundant NAND gates and two interconnection randomizers to restitute the activation fraction of the signal bundles. This structure consists of a first stage performing the NAND operation and a second stage to restore the output value. Restoration is implemented with two NAND operations in series and intercalated randomizing blocks. This restoring unit can be replicated as many times as necessary to improve reliability level, although this implies an additional increase in overhead. Interconnection randomizers consist of elements that randomly connect the output lines of one layer to the following layer's input lines to distribute the errors along with the bundle. Fig. 1 shows the gate level for an NM NAND gate [1]. Parameters usually used to formulate the NAND multiplexing characteristics are: the number of redundant inputs and outputs, the ratio between the faulty input lines and the total number of lines N, the probability of a device producing a faulty output, the number of restoring stages added at the output. Physical implementation for the NAND gates and randomizer blocks is presented in fig 2. This structure has two blocks, which the first one processes the information using a diode-like architecture, and the second one is a CMOS-like inverter that inverts the signal.

Fig.2.Circuit topology used to implement the NAND gates
A Nanodevice based layout for the NAND gate, which is drowned in [1], is presented in Fig. 3 (left). The supply voltage is connected at the top and bottom of the cell, input, and output lines on the sides. The NAND gate is consists of five devices, eleven contacts, and one interconnection. As [1] described, the NAND error probability is: This error probability arises from the individual error probabilities and sizes of each part of the cell. The first parenthesis corresponds to the five devices, the second, third, and fourth parenthesis to contacts 1-3, 4-8, and 9-11, respectively (see Fig. 3 left). The last parenthesis captures the error probability in the interconnection [1].
The randomizer block is built by hardwiring the outputs of one NAND stage to the inputs of the next. To analyze this block, we assume that it is possible to manufacture interconnections with sections D2 of any length. Using the geometric information in Fig. 3 and Fig.  1, [1] estimate the area for an NM NAND gate as: According to Fig.1, NM structure delay is equal to eq. (3). This equation consists of a cascaded delay of three Nand gate. Each Nand gate consists of one dido and one FET transistor, according to Fig 2. Number three is the level of redundancy of the system. As a result, the final formula is equal to eq.4.

Averaging Cell Structure
Structure for the averaging cell gate is that it only replicates the devices (Fig. 4). The layout structure requires a significant connection able to interconnect all the Nanodevices.  Fig. 5 we can observe that the contact areas for any given Nanodevice considerably increase with the redundancy factor (N). The error probability for one individual AND gate (considering that all the parts must be functional) is given by the error probability of the three devices and the six contacts that compose the gate and equivalently for the NOT gate.
Perr AND = 1-(1-P Dev ) 3 (1-β/ND 2 ) 6 (5) Perr NOR = 1-(1-P Dev ) 2 (1-β/ND 2 ) 4 (6) This structure provides a high tolerance for errors in the Nanodevices. However, errors appearing in the interconnection between the two logic functions or defects short-circuiting any Nanocluster are critical. Then, the probability of a critical defect in the structure is approximated in [1] as: Using the dimensions in Fig. 5, [1] estimate the area cost of this gate as: Which has a linear dependence on the redundancy factor N.
According to Fig.4, the AC structure has two parts, diodes part and FETs. As a result, the delay of the AC structure is equal to eq.9.
T AC = T diod + T fet (9) This rate is constant and does not have any dependent on the redundancy. By considering all three parameters of area, reliability, and delay, we can conclude that the AC structure has lower area cost, lower time delay and better reliability in most of the time for designing a fault-tolerant system in the Nanoscale gate. However, NM structure has better reliability for P ErrStr below 0.003 with always larger area cost and time delay in comparison to AC structure.

Conclusion
Redundancy is necessary for the system to designing fault-tolerant structures for the Nanoscale gate in electronic systems. Until now, many methods have been proposed for this purpose, which increases complexity or has an effect on the reliability of the system. In this paper, we compare two methods for designing the fault tolerant structure for Nanoscale gates. These structures are NAND Multiplexing (NM) and Averaging Cells (AC). Simulation results in [1] indicate that AC based gates are more reliable than NM gates for higher error probabilities with lower area cost. Comparing NM and AC in the aspect of delay parameters indicates that AC has a constant delay. Still, the delay of the NM system raises with an increasing level of redundancy. We can conclude that in most cases, the AC structure has lower overhead in delay and area with higher reliability than the NM method for a fault-tolerant system.